RM0453 Rev 5 685/1450
RM0453 AES hardware accelerator (AES)
694
23.7.2 AES status register (AES_SR)
Address offset: 0x04
Reset value: 0x0000 0000
Bits 16, 6:5 CHMOD[2:0]: Chaining mode selection
This bitfield selects the AES chaining mode:
000: Electronic codebook (ECB)
001: Cipher-block chaining (CBC)
010: Counter mode (CTR)
011: Galois counter mode (GCM) and Galois message authentication code (GMAC)
100: Counter with CBC-MAC (CCM)
others: Reserved
Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the
write access and it is not cleared by that write access.
Bits 4:3 MODE[1:0]: AES operating mode
This bitfield selects the AES operating mode:
00: Mode 1: encryption
01: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
10: Mode 3: decryption
11: Reserved
Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the
write access and it is not cleared by that write access.
Bits 2:1 DATATYPE[1:0]: Data type selection
This bitfield defines the format of data written in the AES_DINR register or read from the
AES_DOUTR register, through selecting the mode of data swapping:
00: None
01: Half-word (16-bit)
10: Byte (8-bit)
11: Bit
For more details, refer to Section 23.4.13: AES data registers and data swapping.
Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the
write access and it is not cleared by that write access.
Bit 0 EN: AES enable
This bit enables/disables the AES peripheral:
0: Disable
1: Enable
At any moment, clearing then setting the bit re-initializes the AES peripheral.
This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2)
and upon the completion of GCM/GMAC/CCM initial phase.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BUSY WRERR RDERR CCF
rrrr
Bits 31:4 Reserved, must be kept at reset value.
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