Advanced-control timer (TIM1) RM0453
818/1450 RM0453 Rev 5
25.4.29 TIM1 timer input selection register (TIM1_TISEL)
Address offset: 0x68
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. TI4SEL[3:0] Res. Res. Res. Res. TI3SEL[3:0]
rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. TI2SEL[3:0] Res. Res. Res. Res. TI1SEL[3:0]
rw rw rw rw rw rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 TI4SEL[3:0]: selects TI4[0] to TI4[15] input
0000: TIM1_CH4 input
Others: Reserved
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 TI3SEL[3:0]: selects TI3[0] to TI3[15] input
0000: TIM1_CH3 input
Others: Reserved
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 TI2SEL[3:0]: selects TI2[0] to TI2[15] input
0000: TIM1_CH2 input
Others: Reserved
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input
0000: TIM1_CH1 input
Others: Reserved