System window watchdog (WWDG) RM0453
986/1450 RM0453 Rev 5
As an example, if APB frequency is 48 MHz, WDGTB[2:0] is set to 3 and T[5:0] is set to 63:
Refer to the datasheet for the minimum and maximum values of t
WWDG
.
31.3.6 Debug mode
When the CPU1 enters debug mode (processor halted), the WWDG counter either
continues to work normally or stops, depending on the configuration bit in DBG module. For
more details, refer to Section 38: Debug support (DBG).
31.4 WWDG interrupts
The early wake-up interrupt (EWI) can be used if specific safety operations or data logging
must be performed before the reset is generated. To enable the early wake-up interrupt, the
application must:
• Write EWIF bit of WWDG_SR register to 0, to clear unwanted pending interrupt
• Write EWI bit of WWDG_CFR register to 1, to enable interrupt
When the down-counter reaches the value 0x40, a watchdog interrupt is generated, and the
corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as
communications or data logging), before resetting the device.
In some applications, the EWI interrupt can be used to manage a software system check
and/or system recovery/graceful degradation, without generating a WWDG reset. In this
case the corresponding ISR must reload the WWDG counter to avoid the WWDG reset,
then trigger the required actions.
The watchdog interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note: When the watchdog interrupt cannot be served (for example due to a system lock in a
higher priority task), the WWDG reset is eventually generated.
31.5 WWDG registers
Refer to Section 1.2 on page 59 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by halfwords (16-bit) or words (32-bit).
t
WWDG
1 48000⁄()4096 2
3
×× 63 1+()× 43.69ms==
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