STMicroelectronics STM32WL5 Series User Manual

RM0453 Rev 5 987/1450
RM0453 System window watchdog (WWDG)
988
31.5.1 WWDG control register (WWDG_CR)
Address offset: 0x000
Reset value: 0x0000 007F
31.5.2 WWDG configuration register (WWDG_CFR)
Address offset: 0x004
Reset value: 0x0000 007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. WDGA T[6:0]
rs rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 WDGA: Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter, decremented every
(4096 x 2
WDGTB
[2:0]
) PCLK cycles. A reset is produced when it is decremented from 0x40 to
0x3F (T6 becomes cleared).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. WDGTB[2:0] Res. EWI Res. Res. W[6:0]
rw rw rw rs rw rw rw rw rw rw rw
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:11 WDGTB[2:0]: Timer base
The timebase of the prescaler can be modified as follows:
000: CK counter clock (PCLK div 4096) div 1
001: CK counter clock (PCLK div 4096) div 2
010: CK counter clock (PCLK div 4096) div 4
011: CK counter clock (PCLK div 4096) div 8
100: CK counter clock (PCLK div 4096) div 16
101: CK counter clock (PCLK div 4096) div 32
110: CK counter clock (PCLK div 4096) div 64
111: CK counter clock (PCLK div 4096) div 128
Bit 10 Reserved, must be kept at reset value.

STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English