Section 11: TSP command reference Model 2601B-PULSE System SourceMeter Instrument Reference Manual
11-296 2601B-PULSE-901-01A April 2020
status.operation.instrument.smua.trigger_overrrun.*
This attribute contains the operation status SMU trigger overrun register set.
Usage
operationRegister = status.operation.instrument.smua.trigger_overrun.condition
operationRegister = status.operation.instrument.smua.trigger_overrun.enable
operationRegister = status.operation.instrument.smua.trigger_overrun.event
operationRegister = status.operation.instrument.smua.trigger_overrun.ntr
operationRegister = status.operation.instrument.smua.trigger_overrun.ptr
status.operation.instrument.smua.trigger_overrun.enable = operationRegister
status.operation.instrument.smua.trigger_overrun.ntr = operationRegister
status.operation.instrument.smua.trigger_overrun.ptr = operationRegister
The status of the operation status SMU trigger overrun register; a zero (0) indicates
no bits set (also send 0 to clear all bits); other values indicate various bit settings
Details
These attributes are used to read or write to the operation status SMU trigger overrun registers.
Reading a status register returns a value. The binary equivalent of the returned value indicates which
register bits are set. The least significant bit of the binary number is bit B0, and the most significant bit
is bit B15. For example, if a value of 18 is read as the value of the condition register, the binary
equivalent is 0000 0000 0001 0010. This value indicates that bit B1 and bit B4 are set.
* Least significant bit
** Most significant bit
For information about .condition, .enable, .event, .ntr, and .ptr registers, refer to Status register set
contents (on page 15-1) and Enable and transition registers (on page 15-19). The individual bits of
this register are defined in the following table.
status.operation.instrument.smua.trigger_overrun.ARM
Set bit indicates that the arm event detector of the SMU was already in the detected state when a
trigger was received.
Bit B1 decimal value: 2
status.operation.instrument.smua.trigger_overrun.SRC
Set bit indicates that the source event detector of the SMU was already in the detected state
when a trigger was received.
Bit B2 decimal value: 4