Model 2601B-PULSE System SourceMeter Instrument Reference Manual Section 15: Status model
2601B-PULSE-901-01A April 2020 15-17
The bits of the Status Byte Register are described as follows:
• Bit B0, Measurement Summary Bit (MSB): Set summary bit indicates that an enabled
measurement event has occurred.
• Bit B1, System Summary Bit (SSB): Set summary bit indicates that an enabled system event
has occurred.
• Bit B2, Error Available (EAV): Set bit indicates that an error or status message is present in the
error queue.
• Bit B3, Questionable Summary Bit (QSB): Set summary bit indicates that an enabled
questionable event has occurred.
• Bit B4, Message Available (MAV): Set bit indicates that a response message is present in the
output queue.
• Bit B5, Event Summary Bit (ESB): Set summary bit indicates that an enabled standard event
has occurred.
• Bit B6, Request Service (RQS)/Master Summary Status (MSS): Set bit indicates that an
enabled summary bit of the Status Byte Register is set. Depending on how it is used, bit B6 of the
Status Byte Register is either the Request for Service (RQS) bit or the Master Summary Status
(MSS) bit:
▪ When using the GPIB, USB, or VXI-11 serial poll sequence of the 2601B-PULSE to obtain
the status byte (serial poll byte), B6 is the RQS bit. See Serial polling and SRQ (on page
15-18) for details on using the serial poll sequence.
▪ When using the *STB? common command or status.condition Status byte and service
request commands (on page 15-19) to read the status byte, B6 is the MSS bit.
• Bit B7, Operation Summary (OSB): Set summary bit indicates that an enabled operation event
has occurred.
Service Request Enable Register
The Service Request Enable Register controls the generation of a service request. This register is
programmed by the user and is used to enable or disable the setting of bit B6 (RQS/MSS) by the
Status Summary Message bits (B0, B1, B2, B3, B4, B5, and B7) of the Status Byte Register. As
shown in the Status Byte Register (on page 15-16) topic, a logical AND operation is performed on the
summary bits (&) with the corresponding enable bits of the Service Request Enable Register. When a
logical AND operation is performed with a set summary bit (1) and with an enabled bit (1) of the
enable register, the logic “1” output is applied to the input of the logical OR gate and, therefore, sets
the MSS/RQS bit in the Status Byte Register.
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