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4-16 Performance

AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996

SHR mem, CL 0_1x_1101001x_101_xxx F

ld 1/1

alu1 1/2

st 1/1/3

SHRD reg, reg, imm 1_0x_10101100_xxx_xxx F

alu1 1/1

alu1 2/2

SHRD mem, reg, imm 1_1x_10101100_xxx_xxx M

alu1 1/1

ld 1/1

alu1 2/2

st 2/2/3

SHRD reg, reg, CL 1_0x_10101101_xxx_xxx F

alu1 1/1

alu1 2/2

SHRD mem, reg, CL 1_1x_10101101_xxx_xxx M

alu1 1/1

ld 1/1

alu1 2/2

st 2/2/3

STOS mem, AL/AX/EAX 0_xx_1010101x_xxx_xxx F

st 1/1/3

alu 1/1

SUB reg, reg 0_0x_001010xx_xxx_xxx Falu1/1

SUB reg, mem 0_1x_0010101x_xxx_xxx F

ld 1/1

alu 1/2

SUB mem, reg 0_1x_0010100x_xxx_xxx F

ld 1/1

alu 1/2

st 1/1/3

SUB AL/AX/EAX, imm 0_xx_0010110x_xxx_xxx Falu1/1

SUB reg, imm 0_0x_100000xx_101_xxx Falu 1/1

SUB mem, imm 0_1x_100000xx_101_xxx F

ld 1/1

alu 1/2

st 1/1/3

TEST reg, reg 0_0x_1000010x_xxx_xxx Falu 1/1

TEST mem, reg 0_1x_1000010x_xxx_xxx F

ld 1/1

alu 1/2

TEST reg, imm 0_0x_1111011x_00x_xxx Falu 1/1

TEST AL/AX/EAX, imm 0_xx_1010100x_xxx_xxx Falu 1/1

TEST mem, imm 0_1x_1111011x_00x_xxx F

ld 1/1

alu 1/2

XCHG EAX, reg (except EAX) 0_xx_10010xxx_xxx_xxx F

alu 1/1

alu 2/2

Table 4-1. Integer Instructions (continued)

Instruction Mnemonic Opcode Format

Fastpath or

Microcode

Execution

Unit Timing

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AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm