AMD K5

Dispatch and Execution Timing 4-15
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
SETcc mem 1_1x_1001xxxx_xxx_xxx F
brn 1/1
ld 1/1
st 1/2/3
SHL reg, 1 0_0x_1101000x_1x0_xxx Falu11/1
SHL mem, 1 0_1x_1101000x_1x0_xxx F
ld 1/1
alu1 1/2
st 1/1/3
SHL reg, mem 0_0x_1100000x_1x0_xxx Falu11/1
SHL mem, imm 0_1x_1100000x_1x0_xxx F
ld 1/1
alu1 1/2
st 1/1/3
SHL reg, CL 0_0x_1101001x_1x0_xxx Falu11/1
SHL mem, CL 0_1x_1101001x_1x0_xxx F
ld 1/1
alu1 1/2
st 1/1/3
SHLD reg, reg, imm 1_0x_10100100_xxx_xxx F
alu1 1/1
alu1 2/2
SHLD mem, reg, imm 1_1x_10100100_xxx_xxx M
alu1 1/1
ld 1/1
alu1 2/2
st 2/2/3
SHLD reg, reg, CL 1_0x_10100101_xxx_xxx F
alu1 1/1
alu1 2/2
SHLD mem, reg, CL 1_1x_10100101_xxx_xxx M
alu1 1/1
ld 1/1
alu1 2/2
st 2/2/3
SHR reg, 1 0_0x_1101000x_101_xxx Falu11/1
SHR mem, 1 0_1x_1101000x_101_xxx F
ld 1/1
alu1 1/2
st 1/1/3
SHR reg, mem 0_0x_1100000x_101_xxx Falu11/1
SHR mem, imm 0_1x_1100000x_101_xxx F
ld 1/1
alu1 1/2
st 1/1/3
SHR reg, CL 0_0x_1101001x_101_xxx Falu11/1
Table 4-1. Integer Instructions (continued)
Instruction Mnemonic Opcode Format
Fastpath or
Microcode
Execution
Unit Timing