AMD K5

4-14 Performance
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
ROL reg, 1 0_0x_1101000x_000_xxx Falu11/1
ROL mem, 1 0_1x_1101000x_000_xxx F
ld 1/1
alu1 1/2
st 1/1/3
ROL reg, imm 0_0x_1100000x_000_xxx Falu11/1
ROL mem, imm 0_1x_1100000x_000_xxx F
ld 1/1
alu1 1/2
st 1/1/3
ROL reg, CL 0_0x_1101001x_000_xxx Falu11/1
ROL mem, CL 0_1x_1101001x_000_xxx F
ld 1/1
alu1 1/2
st 1/1/3
ROR reg, 1 0_0x_1101000x_001_xxx Falu11/1
ROR mem, 1 0_1x_1101000x_001_xxx F
ld 1/1
alu1 1/2
st 1/1/3
ROR reg, imm 0_0x_1100000x_001_xxx Falu11/1
ROR mem, imm 0_1x_1100000x_001_xxx F
ld 1/1
alu1 1/2
st 1/1/3
ROR reg, CL 0_0x_1101001x_001_xxx Falu11/1
ROR mem, CL 0_1x_1101001x_001_xxx F
ld 1/1
alu1 1/2
st 1/1/3
SAR reg, 1 0_0x_1101000x_111_xxx Falu11/1
SAR mem, 1 0_1x_1101000x_111_xxx F
ld 1/1
alu1 1/2
st 1/1/3
SAR reg, mem 0_0x_1100000x_111_xxx Falu11/1
SAR mem, imm 0_1x_1100000x_111_xxx F
ld 1/1
alu1 1/2
st 1/1/3
SAR reg, CL 0_0x_1101001x_111_xxx Falu11/1
SAR mem, CL 0_1x_1101001x_111_xxx F
ld 1/1
alu1 1/2
st 1/1/3
SETcc reg 1_0x_1001xxxx_xxx_xxx Fbrn1/1
Table 4-1. Integer Instructions (continued)
Instruction Mnemonic Opcode Format
Fastpath or
Microcode
Execution
Unit Timing