AMD K5

Dispatch and Execution Timing 4-13
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
NOT mem 0_1x_1111011x_010_xxx F
ld 1/1
alu 1/2
st 1/1/3
OR reg, reg 0_0x_000010xx_xxx_xxx Falu1/1
OR reg, mem 0_1x_0000101x_xxx_xxx F
ld 1/1
alu 1/2
OR mem, reg 0_1x_0000100x_xxx_xxx F
ld 1/1
alu 1/2
st 1/1/3
OR AL/AX/EAX, imm 0_xx_0000110x_xxx_xxx Falu1/1
OR reg, imm 0_0x_100000xx_001_xxx Falu 1/1
OR mem, imm 0_1x_100000xx_001_xxx F
ld 1/1
alu 1/2
st 1/1/3
POP reg 0_xx_01011xxx_xxx_xxx F
ld 1/1
alu 1/1
POP reg 0_0x_10001111_000_xxx F
ld 1/1
alu 1/1
POP mem 0_1x_10001111_000_xxx M
ld 1/1
ld 1/1
st 2/2/3
alu 2/2
PUSH reg 0_xx_01010xxx_xxx_xxx F
st 1/1
alu 1/1/2
PUSH reg 0_0x_11111111_110_xxx F
st 1/1
alu 1/1/2
PUSH imm 0_xx_011010x0_xxx_xxx F
alu 1/1
st 1/1/2
alu 1/1
PUSH mem 0_1x_11111111_110_xxx M
ld 1/1
st 1/1/2
alu 1/1
RET near 0_xx_11000011_xxx_xxx F
ld 1/1
alu 1/1
brn 1/2
RET near imm 0_xx_11000010_xxx_xxx M
ld 1/1
alu 1/1
alu 1/2
brn 1/2
Table 4-1. Integer Instructions (continued)
Instruction Mnemonic Opcode Format
Fastpath or
Microcode
Execution
Unit Timing