AMD K5

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AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
Figure 5-24B. Cache-Writeback and Invalidation Cycle
(WBINVD Instruction) Part 2 . . . . . . . . . . . . . . . . . . . . 5-186
Figure 5-25. Branch-Trace Message Cycle . . . . . . . . . . . . . . . . . . . . . 5-188
Figure 5-26A. Transition from Normal Execution to SMM Part 1 . . . 5-190
Figure 5-26B. Transition from Normal Execution to SMM Part 2 . . . 5-191
Figure 5-27A. Stop-Grant and Stop-Clock Modes Part 1 . . . . . . . . . . . 5-193
Figure 5-27B. Stop-Grant and Stop-Clock Modes Part 2 . . . . . . . . . . . 5-194
Figure 5-28. INIT-Initiated Transition from Protected
Mode to Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-196
Figure 6-1. Typical Desktop-System BIOS Memory Map . . . . . . . . . . 6-3
Figure 6-2. Default SMM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Figure 6-3. BOFF
Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Figure 6-4. AHOLD and BOFF
Example . . . . . . . . . . . . . . . . . . . . . . 6-18
Figure 6-5. Write-Once Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Figure 6-6. Clock Control State Transitions. . . . . . . . . . . . . . . . . . . . 6-36
Figure 6-7. V
cc
and CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
Figure 7-1. Hardware Configuration Register (HWCR) . . . . . . . . . . . 7-3
Figure 7-2. Array Access Register (AAR) . . . . . . . . . . . . . . . . . . . . . . 7-8
Figure 7-3. Test Formats: Data-Cache Tags . . . . . . . . . . . . . . . . . . . . 7-10
Figure 7-4. Test Formats: Data-Cache Data . . . . . . . . . . . . . . . . . . . . 7-11
Figure 7-5. Test Formats: Instruction-Cache Tags. . . . . . . . . . . . . . . 7-12
Figure 7-6. Test Formats: Instruction-Cache Instructions . . . . . . . . 7-13
Figure 7-7. Test Formats: 4-Kbyte TLB. . . . . . . . . . . . . . . . . . . . . . . . 7-14
Figure 7-8. Test Formats: 4-Mbyte TLB . . . . . . . . . . . . . . . . . . . . . . . 7-15