AMD K5

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18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
List of Tables
Table 2-1. ALU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Table 2-2. Cache States for Read and Write Accesses . . . . . . . . . . . . 2-19
Table 2-3. Cache States for Snoops, Invalidation,
and Replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Table 2-4. Snoop Action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Table 3-1. Control Register 4 (CR4) Fields . . . . . . . . . . . . . . . . . . . . . . 3-3
Table 3-2. Page-Directory Entry (PDE) Fields . . . . . . . . . . . . . . . . . . . 3-8
Table 3-3. Page-Table Entry (PTE) Fields. . . . . . . . . . . . . . . . . . . . . . 3-11
Table 3-4. Virtual-Interrupt Additions to EFLAGS Register . . . . . . 3-15
Table 3-5A. Instructions that Modify the IF or VIF
Flags—Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Table 3-5B. Instructions that Modify the IF or VIF
Flags—Protected Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Table 3-5C. Instructions that Modify the IF or VIF
Flags—Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
Table 3-5D. Instructions that Modify the IF or
VIF Flags—Virtual-8086 Mode Interrupt
Extensions (VME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Table 3-5E. Instructions that Modify the IF or
VIF Flags—Protected Mode Virtual
Interrupt Extensions (PVI) . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Table 3-6. Interrupt Behavior and Interrupt-Table Access . . . . . . . . 3-23
Table 3-7. Machine-Check Type Register (MCTR) Fields . . . . . . . . . 3-27
Table 3-8. CPU Clock Frequencies, Bus Frequencies,
and P-Rating Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Table 4-1. Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Table 4-2. Integer Dot Product Internal Operations Timing . . . . . . . 4-18
Table 4-3. Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Table 5-1. Summary of Signal Characteristics . . . . . . . . . . . . . . . . . . . 5-4
Table 5-2. Conditions for Driving and Sampling Signals . . . . . . . . . . . 5-8
Table 5-3. Summary of Interrupts and Exceptions. . . . . . . . . . . . . . . 5-16
Table 5-4. Address-Generation Sequence During Bursts. . . . . . . . . . 5-21
Table 5-5. Relation Of BE7
–BE0 To Other Signals . . . . . . . . . . . . . . . 5-34
Table 5-6. Encodings For Special Bus Cycles . . . . . . . . . . . . . . . . . . . 5-35
Table 5-7. Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . 5-36
Table 5-8. Outputs Floated When BOFF
is Asserted . . . . . . . . . . . . . 5-38
Table 5-9. MESI-State Transitions for Reads . . . . . . . . . . . . . . . . . . . 5-51
Table 5-10. Relation Between D63–D0, BE7–BE0
, and DP7–DP0 . . . . 5-56
Table 5-11. MESI-State Transitions for Inquire Cycles . . . . . . . . . . . . 5-71
Table 5-12. Outputs Floated When HLDA is Asserted. . . . . . . . . . . . . 5-74
Table 5-13. Interrupt Acknowledge Operation Definition. . . . . . . . . . 5-85
Table 5-14. PWT, Writeback/Writethrough, and MESI . . . . . . . . . . . 5-105
Table 5-15. Register State After RESET or INIT . . . . . . . . . . . . . . . . 5-110