AMD K5

xiv
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
Table 5-16. Outputs at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-112
Table 5-17. MESI-State Transitions for Reads . . . . . . . . . . . . . . . . . . 5-134
Table 5-18. MESI-State Transitions for Writes . . . . . . . . . . . . . . . . . . 5-135
Table 5-19. Bus Cycle Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136
Table 5-20. Bus-Cycle Order During Misaligned Transfers . . . . . . . . 5-147
Table 5-21. Address-Generation Sequence During Bursts. . . . . . . . . 5-150
Table 5-22. Interrupt Acknowledge Operation Definition. . . . . . . . . 5-175
Table 5-23. Encodings For Special Bus Cycles . . . . . . . . . . . . . . . . . . 5-180
Table 5-24. Branch-Trace Message Special Bus Cycle Fields . . . . . . 5-187
Table 6-1. Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . 6-25
Table 6-2. SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Table 7-1. Hardware Configuration Register (HWCR) Fields. . . . . . . 7-4
Table 7-2. BIST Error Bit Definition in EAX Register . . . . . . . . . . . . . 7-6
Table 7-3. Array IDs in Array Pointers . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Table 7-4. Branch-Trace Message Special Bus Cycle Fields . . . . . . . 7-18
Table 7-5. Test Access Port (TAP) ID Code. . . . . . . . . . . . . . . . . . . . . 7-21
Table 7-6. Public TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22