AMD K5

Bus Cycle Timing 5-191
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 5-26B. Transition from Normal Execution to SMM Part 2
CLK
A31–A3
ADS
BE7–BE0
BRDY
CACHE
D/C
D63–D0
FLUSH
KEN
LOCK
M/IO
SMI
SMIACT
W/R
CLK
Begin save of
processor state