Contents RM0351
12/1830 DocID024597 Rev 5
12.5.7 DMA2D background offset register (DMA2D_BGOR) . . . . . . . . . . . . . 375
12.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . . 376
12.5.9 DMA2D foreground color register (DMA2D_FGCOLR) . . . . . . . . . . . . 378
12.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . 379
12.5.11 DMA2D background color register (DMA2D_BGCOLR) . . . . . . . . . . . 381
12.5.12 DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
12.5.13 DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
12.5.14 DMA2D output PFC control register (DMA2D_OPFCCR) . . . . . . . . . . 382
12.5.15 DMA2D output color register (DMA2D_OCOLR) . . . . . . . . . . . . . . . . . 383
12.5.16 DMA2D output memory address register (DMA2D_OMAR) . . . . . . . . 385
12.5.17 DMA2D output offset register (DMA2D_OOR) . . . . . . . . . . . . . . . . . . 386
12.5.18 DMA2D number of line register (DMA2D_NLR) . . . . . . . . . . . . . . . . . 386
12.5.19 DMA2D line watermark register (DMA2D_LWR) . . . . . . . . . . . . . . . . . 387
12.5.20 DMA2D AHB master timer configuration register (DMA2D_AMTCR) . 387
12.5.21 DMA2D IP version register (DMA2D_VERR) . . . . . . . . . . . . . . . . . . . 387
12.5.22 DMA2D IP identification register (DMA2D_IPIDR) . . . . . . . . . . . . . . . 388
12.5.23 DMA2D IP size identification register (DMA2D_SIDR) . . . . . . . . . . . . 389
12.5.24 DMA2D register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
13 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 392
13.1 NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
13.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
13.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
14 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . 397
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
14.2 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
14.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
14.3.1 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
14.3.2 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
14.3.3 Peripherals asynchronous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 399
14.3.4 Hardware interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
14.3.5 Hardware event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
14.3.6 Software interrupt/event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
14.4 EXTI interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
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