Inter-integrated circuit (I2C) interface RM0453
1094/1450 RM0453 Rev 5
In case of an address match, the I2C stretches SCL low during MCU wake-up time. The
stretch is released when ADDR flag is cleared by software, and the transfer goes on
normally.
If the address does not match, the HSI16 is switched off again and the MCU is not woken
up.
Note: If the I2C clock is the system clock, or if WUPEN = 0, the HSI16 is not switched on after a
START is received.
Only an ADDR interrupt can wake-up the MCU. Therefore do not enter Stop mode when the
I2C is performing a transfer as a master, or as an addressed slave after the ADDR flag is
set. This can be managed by clearing SLEEPDEEP bit in the ADDR interrupt routine and
setting it again only after the STOPF flag is set.
Caution: The digital filter is not compatible with the wake-up from Stop mode feature. If the DNF bit is
not equal to 0, setting the WUPEN bit has no effect.
Caution: This feature is available only when the I2C clock source is the HSI16 oscillator.
Caution: Clock stretching must be enabled (NOSTRETCH = 0) to ensure proper operation of the
wake-up from Stop mode feature.
Caution: If wake-up from Stop mode is disabled (WUPEN = 0), the I2C peripheral must be disabled
before entering Stop mode (PE = 0).
34.4.16 Error conditions
The following errors are the conditions that can cause a communication fail.
Bus error (BERR)
A bus error is detected when a START or a STOP condition is detected and is not located
after a multiple of nine SCL clock pulses. A START or a STOP condition is detected when
an SDA edge occurs while SCL is high.
The bus error flag is set only if the I2C is involved in the transfer as master or addressed
slave (i.e not during the address phase in slave mode).
In case of a misplaced START or RESTART detection in slave mode, the I2C enters
address recognition state like for a correct START condition.
When a bus error is detected, the BERR flag is set in the I2C_ISR register, and an interrupt
is generated if the ERRIE bit is set in the I2C_CR1 register.
Arbitration lost (ARLO)
An arbitration loss is detected when a high level is sent on the SDA line, but a low level is
sampled on the SCL rising edge.
• In master mode, arbitration loss is detected during the address phase, data phase and
data acknowledge phase. In this case, the SDA and SCL lines are released, the
START control bit is cleared by hardware and the master switches automatically to
slave mode.
• In slave mode, arbitration loss is detected during data phase and data acknowledge
phase. In this case, the transfer is stopped, and the SCL and SDA lines are released.
When an arbitration loss is detected, the ARLO flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
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