RM0453 Rev 5 1095/1450
RM0453 Inter-integrated circuit (I2C) interface
1113
Overrun/underrun error (OVR)
An overrun or underrun error is detected in slave mode when NOSTRETCH = 1 and:
• In reception when a new byte is received and the RXDR register has not been read yet.
The new received byte is lost, and a NACK is automatically sent as a response to the
new byte.
• In transmission:
– When STOPF = 1 and the first data byte must be sent. The content of the
I2C_TXDR register is sent if TXE = 0, 0xFF if not.
– When a new byte must be sent and the I2C_TXDR register has not been written
yet, 0xFF is sent.
When an overrun or underrun error is detected, the OVR flag is set in the I2C_ISR register,
and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Packet error checking error (PECERR)
This section is relevant only when the SMBus feature is supported (refer to Section 34.3).
A PEC error is detected when the received PEC byte does not match with the I2C_PECR
register content. A NACK is automatically sent after the wrong PEC reception.
When a PEC error is detected, the PECERR flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Timeout error (TIMEOUT)
This section is relevant only when the SMBus feature is supported (refer to Section 34.3).
A timeout error occurs for any of these conditions:
• TIDLE = 0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this
is used to detect an SMBus timeout.
• TIDLE = 1 and both SDA and SCL remained high for the time defined in the
TIMEOUTA [11:0] bits: this is used to detect a bus idle condition.
• Master cumulative clock low extend time reached the time defined in the
TIMEOUTB[11:0] bits (SMBus t
LOW:MEXT
parameter).
• Slave cumulative clock low extend time reached the time defined in TIMEOUTB[11:0]
bits (SMBus t
LOW:SEXT
parameter).
When a timeout violation is detected in master mode, a STOP condition is automatically
sent.
When a timeout violation is detected in slave mode, SDA and SCL lines are automatically
released.
When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Alert (ALERT)
This section is relevant only when the SMBus feature is supported (refer to Section 34.3).
The ALERT flag is set when the I2C interface is configured as a Host (SMBHEN = 1), the
alert pin detection is enabled (ALERTEN = 1) and a falling edge is detected on the SMBA
pin. An interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
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