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Inter-integrated circuit (I2C) interface RM0453

1096/1450 RM0453 Rev 5

34.4.17 DMA requests

Transmission using DMA

DMA (direct memory access) can be enabled for transmission by setting the TXDMAEN bit

in the I2C_CR1 register. Data is loaded from an SRAM area configured using the DMA

peripheral (see Section 13: Direct memory access controller (DMA)) to the I2C_TXDR

Only the data are transferred with DMA.

• In master mode: the initialization, the slave address, direction, number of bytes and

START bit are programmed by software (the transmitted slave address cannot be

transferred with DMA). When all data are transferred using DMA, the DMA must be

initialized before setting the START bit. The end of transfer is managed with the

NBYTES counter. Refer to Master transmitter.

• In slave mode:

– With NOSTRETCH = 0, when all data are transferred using DMA, the DMA must

be initialized before the address match event, or in ADDR interrupt subroutine,

before clearing ADDR.

– With NOSTRETCH = 1, the DMA must be initialized before the address match

event.

• For instances supporting SMBus: the PEC transfer is managed with NBYTES counter.

Refer to SMBus slave transmitter and SMBus master transmitter.

Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.

Reception using DMA

DMA (direct memory access) can be enabled for reception by setting the RXDMAEN bit in

the I2C_CR1 register. Data is loaded from the I2C_RXDR register to an SRAM area

configured using the DMA peripheral (refer to ) whenever the RXNE bit is set. Only the data

(including PEC) are transferred with DMA.

• In master mode, the initialization, the slave address, direction, number of bytes and

START bit are programmed by software. When all data are transferred using DMA, the

DMA must be initialized before setting the START bit. The end of transfer is managed

with the NBYTES counter.

• In slave mode with NOSTRETCH = 0, when all data are transferred using DMA, the

DMA must be initialized before the address match event, or in the ADDR interrupt

subroutine, before clearing the ADDR flag.

• If SMBus is supported (see Section 34.3): the PEC transfer is managed with the

NBYTES counter. Refer to SMBus Slave receiver and SMBus master receiver.

Note: If DMA is used for reception, the RXIE bit does not need to be enabled.

34.4.18 Debug mode

When the microcontroller enters debug mode (core halted), the SMBus timeout either

continues to work normally or stops, depending on the DBG_I2Cx_ configuration bits in the

DBG module.

STMicroelectronics STM32WL5 Series User Manual

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