RM0453 Rev 5 1339/1450
RM0453 Debug support (DBG)
1435
A DWT comparator compares the value held in its DWT_COMPxR registers with one of the
following:
• a data address
• an instruction address
• a data value
• the cycle count value, for comparator 0 only.
For address matching, the comparator can use a mask, so it matches a range of addresses.
On a successful match, the comparator generates one of the following:
• one or more DWT data trace packets, containing one or more of:
– the address of the instruction that caused a data access
– an address offset, bits[15:0] of the data access address
– the matched data value
• a watchpoint debug event, on either the PC value or the accessed data address
• a CMPMATCH[N] event that signals the match outside the DWT unit
A watchpoint debug event either generates a DebugMonitor exception or causes the
processor to halt execution and enter Debug state.
For more details on how to use the DWT, refer to the Arm
®
v7-M Architecture Reference
Manual [5].
38.6.1 DWT control register (DWT_CTRLR)
Address offset: 0x000
Reset value: 0x4000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NUMCOMP[3:0]
NOTR
CPKT
NOEXT
TRIG
NOCY
CCNT
NOPRF
CNT
Res.
CYCEV
TENA
FOLDE
VTENA
LSUEV
TENA
SLEEP
EVTEN
A
EXCEV
TENA
CPIEV
TENA
EXCTR
CENA
rrrrrrrr rwrwrwrwrwrwrw
1514131211109876543210
Res. Res. Res.
PCSA
MPLEN
A
SYNCTAP[1:0]
CYCTA
P
POSTINIT[3:0] POSTPRESET[3:0]
CYCC
NTENA
rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 NUMCOMP[3:0]: number of comparators implemented (read only)
0x4: Four comparators
Bit 27 NOTRCPKT: trace sampling and exception tracing support (read only)
0: Supported
Bit 26 NOEXTTRIG: external match signal, CMPMATCH support (read only)
0: Supported
Bit 25 NOCYCCNT: cycle counter support (read only)
0: Supported
Bit 24 NOPRFCNT: profiling counter support (read only)
0: Supported
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