Debug support (DBG) RM0453
1428/1450 RM0453 Rev 5
38.14 CPU2 breakpoint unit (BPU)
The BPU allows hardware breakpoints to be set. It contains eight comparators which
monitor the instruction fetch address and return a breakpoint instruction when a match is
detected.The CPU2 PBU does not support flash memory patch functionality.
38.14.1 BPU control register (BPU_CTRLR)
Address offset: 0x000
Reset value: 0x0000 0080
38.14.2 BPU remap register (BPU_REMAPR)
Address offset: 0x004
Reset value: 0x0000 0000
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Res.
NUM_CODE6
NUM_CODE5
NUM_CODE4
NUM_LIT[3:0] NUM_CODE[3:0]
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KEY ENABLE
rrrrrrrrrrr rwrw
Bits 31:15 Reserved, must be kept at reset value.
Bits 11:8 NUM_LIT[3:0]: number of literal address comparators supported (read only)
0x0: No literal comparators supported.
Bit 14,13,12,7,6,5,4 NUM_CODE[6:0]: number of instruction address comparators supported - least significant bits
(read only)
0x8: 8 instruction comparators supported
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 KEY: write protect key
A write to BPU_CTRLR register is ignored if this bit is not set to 1.
Bit 0 ENABLE: BPU enable
0: Disabled
1: Enabled
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RMPSPT
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r
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