RM0453 Rev 5 1429/1450
RM0453 Debug support (DBG)
1435
38.14.3 BPU comparator register x (BPU_COMPxR)
Address offset: 0x008 + 0x004 * x, (x = 0 to 7)
Reset value: 0x0000 0000
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 RMPSPT: Flash memory patch remap
Indicates whether flash memory patch remap is supported (read only).
0: Remapping not supported.
Bits 28:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REPLACE[1:0] Res.
COMP[26:14]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP[13:0]
Res.
ENABL
E
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 REPLACE[1:0]: Defines the behavior when a match occurs between the COMP field and the
instruction fetch address.
0x0: reserved
0x1: Breakpoint on lower half-word, upper half-word is unaffected.
0x2: Breakpoint on upper half-word, lower half-word is unaffected.
0x3: Breakpoint on both upper and lower half-words
Bit 29 Reserved, must be kept at reset value.
Bits 28:2 COMP[26:0]: Value to compare with address bits 28:2 of accesses to instruction code memory
(0x00000000 to 0x1FFFFFFF)
If a match occurs, the action to be taken is defined by the REPLACE field.
Bit 1 Reserved, must be kept at reset value.
Bit 0 ENABLE: comparator enable
The comparator is only enabled if both this bit and the BPU ENABLE bit in the BPU_CTRLR
register are set.
0: Disabled
1: Enabled
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