RM0453 Rev 5 315/1450
RM0453 Reset and clock control (RCC)
371
Bits 27:25 PLLQ[2:0]: Main PLL division factor for PLLQCLK
These bits are set and cleared by software to control the frequency of the main PLL output
clock PLLQCLK. This output can be selected for True RNG clock. These bits can be written
only if PLL is disabled.
PLLQCLK output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 3, 4,... or 8 [VCO
frequency / (N + 1)]
000: reserved
001: PLLQ = 2
010: PLLQ = 3
011: PLLQ = 4
100: PLLQ = 5
101: PLLQ = 6
110: PLLQ = 7
111: PLLQ = 8
Note: The software must set these bits correctly not to exceed 48 MHz on this domain in
range 1.
Bit 24 PLLQEN: Main PLL PLLQCLK output enable
This bit is set and reset by software to enable the PLLQCLK output of the main PLL. In order
to save power, when the PLLQCLK output of the PLL is not used, the value of PLLQEN must
be 0.
0: PLLQCLK output disabled
1: PLLQCLK output enabled
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:17 PLLP[4:0]: Main PLL division factor for PLLPCLK
These bits are set and cleared by software to control the frequency of the main PLL output
clock PLLPCLK. This output can be selected for ADC. These bits can be written only if the
PLL is disabled.
PLLPCLK output clock frequency = VCO frequency / PLLP with PLLP = 2, 3, 4, ...or 32 [VCO
frequency / (N + 1)]
0000: reserved
00001: PLLP = 2
00010: PLLP = 3
00011: PLLP = 4
00100: PLLP = 5
...
11111: PLLP = 32
Caution: The software must set these bits correctly not to exceed 48 MHz on this domain in
range 1.
Bit 16 PLLPEN: Main PLL PLLPCLK output enable
This bit is set and reset by software to enable the PLLPCLK output of the main PLL. In order
to save power, when the PLLPCLK output of the PLL is not used, the value of PLLPEN must
be 0.
0: PLLPCLK output disabled
1: PLLPCLK output enabled
Bit 15 Reserved, must be kept at reset value.
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