RM0453 Rev 5 333/1450
RM0453 Reset and clock control (RCC)
371
7.4.21 RCC APB3 peripheral clock enable register (RCC_APB3ENR)
Address offset: 0x64
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access from
CPU1 is not supported.
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: CPU1 SPI1 clock enable
This bit is set and cleared by software.
0: SPI1 clock disabled for CPU1
1: SPI1 clock enabled for CPU1
Bit 11 TIM1EN: CPU1 TIM1 timer clock enable
This bit is set and cleared by software.
0: TIM1 timer clock disabled for CPU1
1: TIM1P timer clock enabled for CPU1
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCEN: CPU1 ADC clocks enable
This bit is set and cleared by software.
0: ADC bus and kernel clocks disabled for CPU1
1: ADC bus and kernel clocks enabled for CPU1
Bits 8:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SUBGHZSPIEN
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SUBGHZSPIEN: CPU1 sub-GHz radio SPI clock enable
This bit is set and cleared by software.
0: Sub-GHz radio SPI clock disable for CPU1
1: Sub-GHz radio SPI clock enable for CPU1
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