Reset and clock control (RCC) RM0453
334/1450 RM0453 Rev 5
7.4.22 RCC AHB1 peripheral clock enable in Sleep mode register
(RCC_AHB1SMENR)
Address offset: 0x068
Reset value: 0x0000 1007
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res.
CRC
SMEN
Res. Res. Res. Res. Res. Res. Res. Res. Res.
DMAMUX1SMEN
DMA2SMEN
DMA1SMEN
rw rw rw rw
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clock enable during CPU1 CSleep mode.
This bit is set and cleared by software.
0: CRC clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: CRC clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1
CStop mode.
Bits 11:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1SMEN: DMAMUX1 clock enable during CPU1 CSleep mode.
This bit is set and cleared by software.
0: DMAMUX1 clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: DMAMUX1 clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
Bit 1 DMA2SMEN: DMA2 clock enable during CPU1 CSleep mode
This bit is set and cleared by software.
0: DMA2 clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: DMA2 clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
Bit 0 DMA1SMEN: DMA1 clock enable during CPU1 CSleep mode.
This bit is set and cleared by software.
0: DMA1 clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: DMA1 clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode.
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