RM0453 Rev 5 419/1450
RM0453 General-purpose I/Os (GPIO)
431
10.4.18 GPIOC bit set/reset register (GPIOC_BSRR)
Address offset: 0x0818
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15 BR14 BR13 Res. Res. Res. Res. Res. Res. BR6 BR5 BR4 BR3 BR2 BR1 BR0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
1514131211109876543210
BS15 BS14 BS13 Res. Res. Res. Res. Res. Res. BS6 BS5 BS4 BS3 BS2 BS1 BS0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:29 BRy: Port PCy reset output data bit [y] in GPIOC_ODR (y = 15 to 13)
These bits are read clear-write 1. A read to these bits returns the value 0.
0: No action on the corresponding GPIOC_ODR.OD0
1: Resets the corresponding GPIOC_ODR.OD0.
Note: If both BS0 and BR0 are set, BS0 has priority.
Bits 28:23 Reserved, must be kept at reset value.
Bits 22:16 BRy: Port PCy reset output data bit [y] in GPIOC_ODR (y = 6 to 0)
Bits 15:13 BSy: Port PCy set output data bit [y] in GPIOC_ODR (y = 15 to 13)
These bits are read clear-write 1. A read to these bits returns the value 0.
0: No action on the corresponding GPIOC_ODR.OD0
1: Resets the corresponding GPIOC_ODR.OD0.
Note: If both BS0 and BR0 are set, BS0 has priority.
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 BSy: Port PCy set output data bit [y] in GPIOC_ODR (y = 6 to 0)
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