RM0453 Rev 5 425/1450
RM0453 General-purpose I/Os (GPIO)
431
10.4.28 GPIOH output data register (GPIOH_ODR)
Address offset: 0x1C14
Reset value: 0x0000 0000
10.4.29 GPIO H bit set/reset register (GPIOH_BSRR)
Address offset: 0x1C18
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OD3 Res. Res. Res.
rw
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 OD3: Port PH3 output data
This bit can be read and written by software.
Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the
GPIOH_BSRR and GPIOH_BRR registers.
Bits 2:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BR3 Res. Res. Res.
rc_w1
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BS3 Res. Res. Res.
rc_w1
Bits 31:20 Reserved, must be kept at reset value.
Bit 19 BR3: Port PH3 reset output data bit [3] in GPIOH_ODR
This bit is read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOH_ODR.OD3
1: Resets the corresponding GPIOH_ODR.OD3.
Note: If both BS3 and BR3 are set, BS3 has priority.
Bits 18:4 Reserved, must be kept at reset value.
Bit 3 BS3: Port PH3 set output data bit [3] in GPIOH_ODR
This bit is read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOH_ODR.OD3
1: Sets the corresponding GPIOH_ODR.OD3.
Bits 2:0 Reserved, must be kept at reset value.
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