General-purpose I/Os (GPIO) RM0453
426/1450 RM0453 Rev 5
10.4.30 GPIOH configuration lock register (GPIOH_LCKR)
Address offset: 0x1C1C
Reset value: 0x0000 0000
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the lock
sequence has been applied on a port bit, the value of this port bit can no longer be modified
until the next MCU reset or peripheral reset.
Note: A specific write sequence is used to write to the GPIOH_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCK3 Res. Res. Res.
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port PH configuration lock key not active
1: Port PH configuration lock key active. GPIOH_LCKR is locked until the next MCU reset or
peripheral reset.
LOCK key write sequence:
WR LCKR[16] = 1 + LCKR[15:0]
WR LCKR[16] = 0 + LCKR[15:0]
WR LCKR[16] = 1 + LCKR[15:0]
RD LCKR
RD LCKR[16] = 1 (This read operation is optional but it confirms that the lock is active.)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns 1 until the next MCU reset or peripheral reset.
Bits 15:4 Reserved, must be kept at reset value.
Bit 3 LCK3: Port PH3 lock configuration
This bit is read/write but can only be written when the LCKK bit is 0.
0: Port PH3 configuration not locked
1: Port PH3 configuration locked
Bits 2:0 Reserved, must be kept at reset value.
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