RM0453 Rev 5 427/1450
RM0453 General-purpose I/Os (GPIO)
431
10.4.31 GPIOH alternate function low register (GPIOH_AFRL)
Address offset: 0x1C20
Reset value: 0x0000 0000
10.4.32 GPIOH bit reset register (GPIOH_BRR)
Address offset: 0x1C28
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
AFSEL3[3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:12 AFSEL3[3:0]: Port PH3 alternate function selection
These bits are written by software to configure alternate function I/Os.
0x0: AF0 selected
0x1: AF1 selected
0x2: AF2 selected
...
0xE: AF14 selected
0xF: AF15 selected
Bits 11:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BR3 Res. Res. Res.
rc_w1
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 BR3: Port PH3 reset output data bit [3] in GPIOH_ODR
This bit is read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOH_ODR.OD3
1: Resets the corresponding GPIOH_ODR.OD3.
Bits 2:0 Reserved, must be kept at reset value.
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