System configuration controller (SYSCFG) RM0453
438/1450 RM0453 Rev 5
11.2.7 SYSCFG SRAM control and status register (SYSCFG_SCSR)
Address offset: 0x18
Reset value: 0x0000 0000
11.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2)
Address offset: 0x01C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res.
PKASR
AMBSY
Res. Res. Res. Res. Res. Res.
SRAM
BSY
SRAM2
ER
rrrw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 PKASRAMBSY: PKA SRAM busy by erase operation
0: No PKA SRAM erase operation is ongoing.
1: PKA SRAM erase operation is ongoing.
See Section 2.4: SRAM erase for more information on SRAM erase conditions
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 SRAMBSY: SRAM1 or SRAM2 busy by erase operation
0: No SRAM1 or SRAM2 erase operation is ongoing.
1: SRAM1 or SRAM2 erase operation is ongoing.
See Section 2.4: SRAM erase for more information on SRAM erase conditions
Bit 0 SRAM2ER: SRAM2 erase
Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at
the end of the SRAM2 erase operation.
Note: This bit is write-protected: setting this bit is possible only after the correct key sequence
is written in the SYSCFG_SKR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. SPF Res. Res. Res. Res. ECCL PVDL SPL CLL
rc_w1 rsrsrsrs
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 SPF: SRAM2 parity error flag
This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software
by writing ‘1’.
0: No SRAM2 parity error detected
1: SRAM2 parity error detected
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