STMicroelectronics STM32WL5 Series - Page 467

RM0453 Rev 5 467/1450
RM0453 Direct memory access controller (DMA)
479
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 TEIF7: Transfer error (TE) flag for channel 7
0: No TE event
1: A TE event occurred.
Bit 26 HTIF7: Half transfer (HT) flag for channel 7
0: No HT event
1: An HT event occurred.
Bit 25 TCIF7: Transfer complete (TC) flag for channel 7
0: No TC event
1: A TC event occurred.
Bit 24 GIF7: Global interrupt flag for channel 7
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 23 TEIF6: Transfer error (TE) flag for channel 6
0: No TE event
1: A TE event occurred.
Bit 22 HTIF6: Half transfer (HT) flag for channel 6
0: No HT event
1: An HT event occurred.
Bit 21 TCIF6: Transfer complete (TC) flag for channel 6
0: No TC event
1: A TC event occurred.
Bit 20 GIF6: Global interrupt flag for channel 6
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 19 TEIF5: Transfer error (TE) flag for channel 5
0: No TE event
1: A TE event occurred.
Bit 18 HTIF5: Half transfer (HT) flag for channel 5
0: No HT event
1: An HT event occurred.
Bit 17 TCIF5: Transfer complete (TC) flag for channel 5
0: No TC event
1: A TC event occurred.
Bit 16 GIF5: Global interrupt flag for channel 5
0: No TE, HT, or TC event
1: a TE, HT, or TC event occurred.
Bit 15 TEIF4: Transfer error (TE) flag for channel 4
0: No TE event
1: A TE event occurred.
Bit 14 HTIF4: Half transfer (HT) flag for channel 4
0: No HT event
1: An HT event occurred.