STMicroelectronics STM32WL5 Series - Page 468

Direct memory access controller (DMA) RM0453
468/1450 RM0453 Rev 5
Bit 13 TCIF4: Transfer complete (TC) flag for channel 4
0: No TC event
1: A TC event occurred.
Bit 12 GIF4: Global interrupt flag for channel 4
0: No TE, HT, or TC event
1:A TE, HT, or TC event occurred.
Bit 11 TEIF3: Transfer error (TE) flag for channel 3
0: No TE event
1: A TE event occurred.
Bit 10 HTIF3: Half transfer (HT) flag for channel 3
0: No HT event
1: An HT event occurred.
Bit 9 TCIF3: Transfer complete (TC) flag for channel 3
0: no TC event
1: A TC event occurred.
Bit 8 GIF3: Global interrupt flag for channel 3
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 7 TEIF2: Transfer error (TE) flag for channel 2
0: No TE event
1: A TE event occurred.
Bit 6 HTIF2: Half transfer (HT) flag for channel 2
0: No HT event
1: An HT event occurred.
Bit 5 TCIF2: Transfer complete (TC) flag for channel 2
0: No TC event
1: A TC event occurred.
Bit 4 GIF2: Global interrupt flag for channel 2
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 3 TEIF1: Transfer error (TE) flag for channel 1
0: No TE event
1: A TE event occurred.
Bit 2 HTIF1: Half transfer (HT) flag for channel 1
0: No HT event
1: An HT event occurred.
Bit 1 TCIF1: Transfer complete (TC) flag for channel 1
0: No TC event
1: A TC event occurred.
Bit 0 GIF1: Global interrupt flag for channel 1
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.