Direct memory access controller (DMA) RM0453
470/1450 RM0453 Rev 5
13.6.3 DMA channel x configuration register (DMA_CCRx)
Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
This register contains secure and privileged information: the secure state and the privileged
state of the channel x (SECM and PRIV control bits).
Modifying the SECM bit must be performed by a secure write access to this register.
Modifying the PRIV bit must be performed by a privileged write access to this register.
Bit 20 CGIF6: Global interrupt flag clear for channel 6
Bit 19 CTEIF5: Transfer error flag clear for channel 5
Bit 18 CHTIF5: Half transfer flag clear for channel 5
Bit 17 CTCIF5: Transfer complete flag clear for channel 5
Bit 16 CGIF5: Global interrupt flag clear for channel 5
Bit 15 CTEIF4: Transfer error flag clear for channel 4
Bit 14 CHTIF4: Half transfer flag clear for channel 4
Bit 13 CTCIF4: Transfer complete flag clear for channel 4
Bit 12 CGIF4: Global interrupt flag clear for channel 4
Bit 11 CTEIF3: Transfer error flag clear for channel 3
Bit 10 CHTIF3: Half transfer flag clear for channel 3
Bit 9 CTCIF3: Transfer complete flag clear for channel 3
Bit 8 CGIF3: Global interrupt flag clear for channel 3
Bit 7 CTEIF2: Transfer error flag clear for channel 2
Bit 6 CHTIF2: Half transfer flag clear for channel 2
Bit 5 CTCIF2: Transfer complete flag clear for channel 2
Bit 4 CGIF2: Global interrupt flag clear for channel 2
Bit 3 CTEIF1: Transfer error flag clear for channel 1
Bit 2 CHTIF1: Half transfer flag clear for channel 1
Bit 1 CTCIF1: Transfer complete flag clear for channel 1
Bit 0 CGIF1: Global interrupt flag clear for channel 1
To Next Page
Loading...
Need help?
General
