RM0453 Rev 5 885/1450
RM0453 General-purpose timer (TIM2)
892
26.4.15 TIM2 auto-reload register (TIM2_ARR)
Address offset: 0x2C
Reset value: 0xFFFF FFFF
26.4.16 TIM2 capture/compare register 1 (TIM2_CCR1)
Address offset: 0x34
Reset value: 0x0000 0000
26.4.17 TIM2 capture/compare register 2 (TIM2_CCR2)
Address offset: 0x38
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 ARR[31:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 26.3.1: Time-base unit on page 824 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 CCR1[31:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1). The
TIMx_CCR1 register is read-only and cannot be programmed.
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