RM0453 Rev 5 1345/1450
RM0453 Debug support (DBG)
1435
38.6.12 DWT CoreSight peripheral identity register 4 (DWT_PIDR4)
Address offset: 0xFD0
Reset value: 0x0000 0004
38.6.13 DWT CoreSight peripheral identity register 0 (DWT_PIDR0)
Address offset: 0xFE0
Reset value: 0x0000 0002
Bit 5 EMITRANGE: Enables generation of data trace address offset packets (containing data
address bits 0 to 15).
0x0: Disabled
0x1: Enabled
Bit 4 Reserved, must be kept at reset value.
Bits 3:0 FUNCTION[3:0]: Selection of action to take on comparator match
The meaning of this bit field depends on the setting of the DATAVMATCH and CYCMATCH
fields. See [5].
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. F4KCOUNT[3:0] JEP106CON[3:0]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 F4KCOUNT[3:0]: register file size
0x0: Register file occupies a single 4-Kbyte region.
Bits 3:0 JEP106CON[3:0]: JEP106 continuation code
0x4: Arm
®
JEDEC code
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PARTNUM[7:0]: part number bits [7:0]
0x02: DWT part number