RM0453 Rev 5 1419/1450
RM0453 Debug support (DBG)
1435
38.13.6 CPU2 ROM1 CoreSight peripheral identity register 3
(C2ROM1_PIDR3)
Address offset: 0xFEC
Reset value: 0x0000 0000
38.13.7 CPU2 ROM1 CoreSight component identity register 0
(C2ROM1_CIDR0)
Address offset: 0xFF0
Reset value: 0x0000 000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 REVAND[3:0]: metal fix version
0x0: No metal fix
Bits 3:0 CMOD[3:0]: customer modified
0x0: No customer modifications
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[7:0]: component ID bits [7:0]
0x0D: Common ID value
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