System configuration controller (SYSCFG) RM0453
440/1450 RM0453 Rev 5
11.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR)
Address offset: 0x024
Reset value: 0x0000 0000
11.2.11 SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1)
Address offset: 0x100
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. KEY[7:0]
wwwwwwww
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase
The following steps are required to unlock the write protection of the SRAM2ER bit in the
SYSCFG_SCSR register.
1. Write 0xCA into Key[7:0].
2. Write 0x53 into Key[7:0].
Writing a wrong key reactivates the write protection.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI15
IM
EXTI14
IM
EXTI13
IM
EXTI12
IM
EXTI11I
M
EXTI10
IM
EXTI9I
M
EXTI8I
M
EXTI7I
M
EXTI6I
M
EXTI5I
M
Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RTCSS
RUIM
Res.
RTCST
AMPTA
MPLSE
CSSIM
rw rw
Bits 31:21 EXTIxIM: EXTIx interrupt mask to CPU1 (x = 15 to 5)
0: EXTIx interrupt forwarded to CPU1
1. EXTIx interrupt to CPU1 masked
Bits 20:3 Reserved, must be kept at reset value.
Bit 2 RTCSSRUIM: RTC SSRU interrupt mask to CPU1
0: RTC SSRU interrupt forwarded to CPU1
1. RTC SSRU interrupt to CPU1 masked
Bit 1 Reserved, must be kept at reset value.
Bit 0 RTCSTAMPTAMPLSECSSIM: RTCSTAMPTAMPLSECSS interrupt mask to CPU1
0: RTCSTAMPTAMPLSECSS interrupt forwarded to CPU1
1. RTCSTAMPTAMPLSECSS interrupt to CPU1 masked
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