MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
22-26 Freescale Semiconductor
22.4.4 Message Buffer Handling
In order to maintain data coherency and FlexCAN2 proper operation, the CPU must obey the rules
described in Section 22.4.2, “Transmit Process,” and Section 22.4.3, “Receive Process.” Any form of CPU
accessing a MB structure within FlexCAN2 other than those specified can cause FlexCAN2 to behave in
an unpredictable way.
Deactivation of a message buffer is a CPU action that causes that MB to be excluded from FlexCAN2
transmit or receive processes during the current match/arbitration round. Any CPU write access to a
control and status word of the MB structure deactivates that MB, excluding it from the current RX/TX
process. However, deactivation is not permanent. The MB that was deactivated during the current
match/arbitration round will be available for transmission or reception in the next round.
The purpose of deactivation is data coherency. The match/arbitration process scans the MBs to decide
which MB to transmit or receive. If the CPU updates the MB in the middle of a match or arbitration
process, the data of that MB may no longer be coherent, therefore that MB is deactivated.
Match and arbitration are one-pass processes. After scanning all MBs, a winner is determined. If MBs are
changed after they are scanned, no re-evaluation is done to determine a new match/winner; and a frame
may be lost because the winner may have been deactivated. If two RX MBs have a matching ID to a
received frame, then it is not guaranteed reception if the user deactivated the matching MB after
FlexCAN2 has scanned the second.
22.4.4.1 Notes on TX Message Buffer Deactivation
There is a point in time until which the deactivation of a TX MB causes it not to be transmitted (end of
move out). After this point, it is transmitted but no interrupt is issued and the CODE field is not updated.
If a TX MB containing the lowest ID (or lowest buffer if LBUF is set) is deactivated after FlexCAN2 has
scanned it while in arbitration process, then FlexCAN2 can transmit a MB with ID that may not be the
lowest at the time.
22.4.4.2 Notes on RX Message Buffer Deactivation
If the deactivation occurs during move in, the move operation is aborted and no interrupt is issued, but the
MB contains mixed data from two different frames.
In case the CPU writes data into RX MB data words while it is being moved in, the move operation is
aborted and no interrupt will be issued, but the control/status word may be changed to reflect FULL or
OVRN. This action should be avoided.
22.4.4.3 Data Coherency Mechanisms
The FlexCAN2 module has a mechanism to assure data coherency in both receive and transmit processes.
The mechanism includes a lock status for MBs and two internal storage areas, called serial message buffers
(SMB), to buffer frame transfers within FlexCAN. The details of the mechanism are the following:
• CPU reading a control and status word of an MB triggers a lock for that MB; that is, a new RX
frame which matches this MB, cannot be written into this MB.
• In order to release a locked MB, the CPU should either lock another MB (by reading its control and
status word), or globally release any locked MB (by reading the free-running timer).
• If while a MB is locked, an RX frame with a matching ID is received, then it cannot be stored
within that MB and it remains in the SMB. There is no indication in the CANx_ESR of that
situation.
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