Freescale Semiconductor MPC5553 - Order of Execution

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
10-36 Freescale Semiconductor
10.5.4 Order of Execution
An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors
associated with each of their peripheral or software settable interrupt requests. However, if multiple
peripheral or software settable interrupt requests are asserted, more than one has the highest priority, and
that priority is high enough to cause preemption, the INTC selects the one with the lowest unique vector
regardless of the order in time that they asserted. However, the ability to meet deadlines with this
scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software
settable interrupt requests asserted.
The example in Table 10-10 shows the order of execution of both ISRs with different priorities and the
same priority.
Table 10-10. Order of ISR Execution Example
Step Step Description
Code Executing At End of Step
PRI in
INTC_CPR
at End of
Step
RTOS ISR108
1
ISR208 ISR308 ISR408
Interrupt
Exception
Handler
1 RTOS at priority 0 is executing. X 0
2 Peripheral interrupt request 100
at priority 1 asserts. Interrupt
taken.
X1
3 Peripheral interrupt request 400
at priority 4 is asserts. Interrupt
taken.
X4
4 Peripheral interrupt request 300
at priority 3 is asserts.
X4
5 Peripheral interrupt request 200
at priority 3 is asserts.
X4
6 ISR408 completes. Interrupt
exception handler writes to
INTC_EOIR.
X1
7 Interrupt taken. ISR208 starts to
execute, even though peripheral
interrupt request 300 asserted
first.
X3
8 ISR208 completes. Interrupt
exception handler writes to
INTC_EOIR.
X1
9 Interrupt taken. ISR308 starts to
execute.
X3
10 ISR308 completes. Interrupt
exception handler writes to
INTC_EOIR.
X1