Freescale Semiconductor MPC5553 - Overview

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 14-3
14.1.2 Overview
The Ethernet media access controller (MAC) is designed to support both 10 and 100 Mbps
Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required
to complete the interface to the media. The FEC supports three different standard MAC-PHY (physical)
interfaces for connection to an external Ethernet transceiver. The FEC supports the 10/100 Mbps MII and
the 10 Mbps-only 7-wire interface, which uses a subset of the MII signals.
The descriptor controller is a RISC-based controller that provides the following functions in the FEC:
• Initialization (those internal registers not initialized by the user or hardware)
• High level control of the DMA channels (initiating DMA transfers)
• Interpreting buffer descriptors
• Address recognition for receive frames
• Random number generation for transmit collision backoff timer
NOTE
DMA references in this section refer to the FEC’s DMA engine. This DMA
engine is for the transfer of FEC data only, and is not related to the DMA
controller described in Chapter 9.
The RAM is the focal point of all data flow in the fast Ethernet controller and is divided into transmit and
receive FIFOs. The FIFO boundaries are programmable using the FRSR register. User data flows to/from
the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the
transmit block and receive data flows from the receive block into the receive FIFO.
The user controls the FEC by writing, through the SIF (slave interface) module, into control registers
located in each block. The CSR (control and status register) block provides global control (e.g. Ethernet
reset and enable) and interrupt handling registers.
The MII block provides a serial channel for control/status communication with the external physical layer
device (transceiver). This serial channel consists of the FEC_MDC (management data clock) and
FEC_MDIO (management data input/output) lines of the MII interface.
The DMA block provides multiple channels allowing transmit data, transmit descriptor, receive data, and
receive descriptor accesses to run independently.
The transmit and receive blocks provide the Ethernet MAC functionality (with some assist from
microcode).
The message information block (MIB) maintains counters for a variety of network events and statistics. It
is not necessary for operation of the FEC but provides valuable counters for network management. The
counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE 802.3
counters.