Freescale Semiconductor MPC5553 - External Signal Description

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
4-2 Freescale Semiconductor
the specified location and uses the RCHW value to determine and execute the specified boot procedure.
See Section 4.4.3, “Reset Configuration and Configuration Pins,” for a complete description.
4.2 External Signal Description
4.2.1 Reset Input (RESET)
The RESET pin is an active low input that is asserted by an external device during a power-on or external
reset. The internal reset signal asserts only if the RESET pin is asserted for 10 clock cycles. Assertion of
the RESET pin while the device is in reset causes the reset cycle to start over. The RESET pin also has an
associated glitch detector which detects spikes greater than 2 clocks in duration that fall below the switch
point of the input buffer logic.
4.2.2 Reset Output (RSTOUT)
The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven
to the low state by the MCU for all internal and external reset sources.
After the negation of the RESET input, if the PLL is configured for 1:1 (dual controller) mode or bypass
mode, the RSTOUT signal is asserted for 16000 clocks, plus 4 clocks for sampling of the configuration
pins. If the PLL is configured for any other operating mode, the RSTOUT signal is asserted for 2400
clocks, plus 4 clocks for sampling of the configuration pins. See Section 11.1.4, “FMPLL Modes of
Operation” for details of PLL configuration.
The RSTOUT pin can also be asserted by a write to the SER bit of the system reset control register
(SIU_SRCR).
NOTE
During a power on reset, RSTOUT is three-stated.
4.2.3 Reset Configuration (RSTCFG)
The RSTCFG input is used to enable the BOOTCFG[0:1] and PLLCFG[0:1] pins during reset. If RSTCFG
is negated during reset, the BOOTCFG and PLLCFG pins are not sampled at the negation of RSTOUT. In
that case, the default values for BOOTCFG and PLLCFG are used. If RSTCFG
is asserted during reset,
the values on the BOOTCFG and PLLCFG pins are sampled and configure the boot and FMPLL modes.
In the 208 package there is no RSTCFG
pin; this signifies that external bus access is not available in this
package. Subsequently, PLLCFG[0] and BOOTCFG[1] are always sampled at reset, meaning that the 208
package does not reset to the crystal reference mode. See Section 4.4.3.3.1, “BOOTCFG[0:1]
Configuration in the 208 Package and Section 4.4.3.4, “PLLCFG[0:1] Pins for more information.
4.2.4 Weak Pull Configuration (WKPCFG)
WKPCFG determines whether specified eTPU and EMIOS pins are connected to a weak pull up or weak
pull down during and immediately after reset.