Freescale Semiconductor MPC5553 - RAM ECC Address Register (ECSM_REAR)

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 8-11
8.2.1.11 RAM ECC Address Register (ECSM_REAR)
The ECSM_REAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in
the RAM memory. Depending on the state of the ECSM_ECR, an ECC event in the RAM causes the
address, attributes and data associated with the access to be loaded into the ECSM_REAR, ECSM_REMR,
ECSM_REAT and ECSM_REDRs, and the appropriate flag (RNCE) in the ECSM_ESR to be asserted.
0123456789101112131415
RFEDL
W
ResetUUUUUUUUUUUUUUUU
Reg Addr Base + 0x5C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RFEDL
W
ResetUUUUUUUUUUUUUUUU
Reg Addr Base + 000x5C
1
“U” signifies a bit that is uninitialized.
Figure 8-8. Flash ECC Data Low Register (ECSM_FEDRL)
Table 8-10. ECSM_FEDRL Field Descriptions
Bits Name Description
0–31 FEDL
[0:31]
Flash ECC data. Contains the data associated with the faulting access of the last,
properly-enabled flash ECC event. The register contains the data value taken directly from
the data bus. The reset value of this field is undefined.
0123456789101112131415
R REAR
W
ResetUUUUUUUUUUUUUUUU
Reg Addr Base + 0x0060
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R REAR
W
ResetUUUUUUUUUUUUUUUU
Reg Addr Base + 0x0060
1
“U” signifies a bit that is uninitialized.
Figure 8-9. RAM ECC Address Register (ECSM_REAR)