MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 20-65
3. The setting of the EOQF flag will disable both serial transmission, and serial reception of data,
putting the DSPI in the STOPPED state. The TXRXS bit is negated to indicate the STOPPED
state.
4. The eDMA will continue to fill TX FIFO until it is full or step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel
assigned to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable
request bits in the eDMA controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the
RXCNT in DSPIx_SR or by checking RFDF in the DSPIx_SR after each read operation of the
DSPIx_POPR.
7. Modify DMA descriptor of TX and RX channels for “new” queues.
8. Flush TX FIFO by writing a 1 to the CLR_TXF bit in the DSPIx_MCR, Flush RX FIFO by
writing a 1 to the CLR_RXF bit in the DSPIx_MCR.
9. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the
new queue or via CPU writing directly to SPI_TCNT field in the DSPIx_TCR.
10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the
DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit.
11. Enable serial transmission and serial reception of data by clearing the EOQF bit.
20.5.2 Baud Rate Settings
Table 20-31 shows the baud rate that is generated based on the combination of the baud rate prescaler PBR
and the baud rate scaler BR in the DSPIx_CTARs. The values calculated assume a 100 MHz system
frequency.
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