MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 11-33
11.5 Revision History
Table 11-12. Changes to MPC5553/5554 RM Rev. 4.0 Release
Description of Change
• In the Features list, made this change:
From: “range from 48MHz to 132MHz “
To: “range from 48MHz to maximum device frequency”
• In the
Software Controlled Power Management/Clock Gating Support Table 11-7, the eTPU_B row is shaded to
indicate that it is on MPC5554.
•In Section 11.4.2.2, “Reduced Frequency Divider (RFD)”:
From: “The RFD must be programmed to be 1 when changing MFD or PREDIV or when enabling frequency modulation”
To: “To protect the system from frequency overshoot during the PLL lock detect phase, the RFD must be programmed to
be 1 when changing MFD or PREDIV or when enabling frequency modulation.”
•In Section 11.4.2.6.1, “Alternate/Backup Clock Selection,” made this change:
From: “Note that when the FMPLL is operated in SCM the system frequency is dependent upon the value in RFD[0:2].”
To: “Note that when the FMPLL is operated in SCM, writes to FMPLL_SYNCR[RFD] have no effect on clock frequency. “
•In Section 11.4.3.1, “Programming System Clock Frequency Without Frequency Modulation” section, added this note:
“When using crystal reference mode or external reference mode, The PREDIV value must not be set to any value that
causes the phase/frequency detector to go below 4 MHz. That is, the crystal or external clock frequency divided by the
PREDIV value must be in the range of 4 MHz – 20 MHz.”
• Changed value of ENGCLK divider factors
from: 2 to 128
to: 2 to 126
• Modified the LOCK bit to read:
PLL lock status bit. Indicates whether the FMPLL has acquired lock. If the LOCK bit is read when the FMPLL
simultaneously loses lock or acquires lock, the bit does not reflect the current condition of the FMPLL.
If operating in bypass mode, LOCK remains cleared after reset. Refer to the frequency as defined in the MPC5553
Microcontroller Datasheet and MPC5554 Microcontroller Datasheet for the lock/unlock range.
0 PLL is unlocked.
1 PLL is locked.
• Made changes in LOCKS bit:
From “a write to the FMPLL_SYNCR which modifies the MFD bits”
To: a write to the FMPLL_SYNCR which modifies the MFD and PREDIV bits”
• Added the symbols F
ref_crystal
and F
ref_ext
to the diagrams, and throughout the manual added further explanation of the fact
that F
prediv
is the frequency after the predivider.
• Modified Table 11-8 “Input Clock Frequency” by adding a column of frequency symbols.
• Modified Table 11-10 “Clock Out vs Clock In Relationships” by changing F
ref
symbols to F
ref_crystal
and F
ref_ext
.
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