MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 13-37
After reset is negated, register accesses can be performed, although it should be noted that registers that
require updating from shadow information, or other inputs, cannot read updated values until flash exits
reset. FLASH_MCR[DONE] may be polled to determine if reset has been exited.
13.5 Revision History
Table 13-19. Changes to MPC5553/5554 RM for Rev. 4.0 Release
Description of Change
• In the Overview section, made this change:
From: “...and a 256-bit read data interface to flash memory. If enabled, the FBIU contains a two-entry, 256-bit prefetch
buffer and a prefetch controller that prefetches sequential lines of data from the flash array into the buffer. Prefetch buffer
hits allow no-wait responses. Normal flash array accesses are registered in the FBIU and are forwarded to the system
bus on the following cycle, ...”
To: “...and a 256-bit read data interface from the flash memory array. If enabled, the FBIU contains a two-entry prefetch
buffer, each entry containing 256 bits of data, and an associated controller that prefetches sequential lines of data from
the flash array into the buffer. Prefetch buffer hits support zero-wait responses. Normal flash array accesses (i.e. those
accesses that do not hit in the prefetch buffers) are registered in the FBIU and are forwarded to the system bus on the
following cycle,...”
Table 13-20. Changes to MPC5553/5554 RM for Rev. 5.0 Release
Description of Change
No change for Rev. 5 release.
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