Freescale Semiconductor MPC5553 - MPC5553-Specific Modules

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 1-11
• POR block
— Provides initial reset condition up to the voltage at which pins (RESET) can be read safely. It
does not guarantee the safe operation of the chip at specified minimum operating voltages.
1.3 MPC5553-Specific Modules
The MPC5553 has two modules not found on the MPC5554, a fast Ethernet controller (FEC) module and
a calibration bus:
• Fast Ethernet controller (MPC5553 only)
— Built-in FIFO and DMA controller
— Fully software compatible to the FEC module of Freescale's industry standard PowerQUICC
communications controller
—IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition)
— Built-in FIFO and DMA controller
— Support for different Ethernet physical interfaces:
– 100Mbps IEEE 802.3 MII
– 10Mbps IEEE 802.3 MII
– 10Mbps 7-wire interface (industry standard)
— MII management interface for control and status
— Large on-chip transmit and receive Fifes to support a variety of bus latencies
— Retransmission from the transmit FIFO after a collision
— Automatic internal flushing of the receive FIFO for runts and collisions
— External BD tables of user-definable size allow nearly unlimited flexibility in management of
transmit and receive buffer memory
— Address recognition for broadcast, single-station address, promiscuous mode, and multicast
hashing
— Ethernet channel uses DMA burst transactions to transfer data to and from external/system
memory
• Partial calibration interface (MPC5553 Only)
— 1.8
–3.3 V I/O nominal voltage
— Memory controller shared with EBI
— 16-bit calibration data bus shared with the upper 16 bits of the data bus
— 21-bit address bus with the least significant address bit (ADDR31) being not supported:
– CAL_ADDR[10:11] shared with CAL_CS[2:3]
– CAL_ADDR[12:26] shared with ADDR[12:26]
– CAL_ADDR[27:30]
— Up to 22 bit address space providing a 4 Mbyte addressing range (the most significant two bits
shared with CAL_CS[2:3])
— Chip selects: up to three chip selects – CAL_CS
0 and CAL_CS[2:3]