Freescale Semiconductor MPC5553 - Register Definition

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 24-5
24.3 Register Definition
This section provides a detailed description of the JTAGC registers accessible through the TAP interface,
including data registers and the instruction register. Individual bit-level descriptions and reset states of
each register are included. These registers are not memory-mapped and can only be accessed through the
TAP.
24.3.1 Register Descriptions
The JTAGC registers are described in this section.
24.3.1.1 Instruction Register
The JTAGC uses a 5-bit instruction register as shown in Figure 24-2. The instruction register allows
instructions to be loaded into the module to select the test to be performed or the test data register to be
accessed or both. Instructions are shifted in through TDI while the TAP controller is in the Shift-IR state,
and latched on the falling edge of TCK in the Update-IR state. The latched instruction value can only be
changed in the Update-IR and Test-Logic-Reset TAP controller states. Synchronous entry into the
test-logic-reset state results in the IDCODE instruction being loaded on the falling edge of TCK.
Asynchronous entry into the test-logic-reset state results in asynchronous loading of the IDCODE
instruction. During the capture-IR TAP controller state, the instruction shift register is loaded with the
value 0b10101, making this value the register’s read value when the TAP controller is sequenced into the
Shift-IR state.
24.3.1.2 Bypass Register
The bypass register is a single-bit shift register path selected for serial data transfer between TDI and TDO
when the BYPASS, CLAMP, HIGHZ or reserve instructions are active. After entry into the capture-DR
state, the single-bit shift register is set to a logic 0. Therefore, the first bit shifted out after selecting the
bypass register is always a logic 0.
24.3.1.3 Device Identification Register
The device identification register, shown in Figure 24-3, allows the part revision number, design center,
part identification number, and manufacturer identity code to be determined through the TAP. The device
identification register is selected for serial data transfer between TDI and TDO when the IDCODE
instruction is active. Entry into the capture-DR state while the device identification register is selected
loads the IDCODE into the shift register to be shifted out on TDO in the Shift-DR state. No action occurs
in the update-DR state.
43210
R 1 0 1 0 1
W Instruction Code
Reset00001
Figure 24-2. 5-Bit Instruction Register