MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
25-66 Freescale Semiconductor
25.11.15.7.2 Access Termination
The following cases are defined for sequences of the read/write protocol that differ from those described
in the above sections:
1. If the AC bit in the RWCS register is set to start read/write accesses and invalid values are loaded
into the RWD and/or RWA, then a system bus access error may occur. This is handled as described
above.
2. If a block access is in progress (all cycles not completed), and the RWCS register is written, then
the original block access is terminated at the boundary of the nearest completed access.
a) If the RWCS is written with the AC bit set, the next read/write access will begin and the RWD
can be written to/ read from.
b) If the RWCS is written with the AC bit cleared, the read/write access is terminated at the
nearest completed access. This method can be used to break (early terminate) block accesses.
25.11.15.8 Read/Write Access Error Message
The read/write access error message is sent out when an system bus access error (read or write) has
occurred.
Error information is messaged out in the following format:
Figure 25-51. Error Message Format
25.11.16 Examples
The following are examples of program trace and data trace messages.
Table 25-39 illustrates an example indirect branch message with an 8 MDO / 2 MSEO configuration.
Note that T0 and S0 are the least significant bits where:
• Tx = TCODE number (fixed)
• Sx = Source processor (fixed)
• Ix = Number of instructions (variable)
• Ax = Unique portion of the address (variable)
Table 25-39. Indirect Branch Message Example (12 MDO / 2 MSEO)
Clock
MDO[11:0]
MSEO[1:0] State
11109876543210
0 XXXXXXXXXXXX 1 1Idle (or end of last
message)
1 I1 I0S3S2S1S0T5T4T3T2T1T0 0 0Start Message
ECODE (00011)
msb lsb
12
SRC TCODE (001000)
3
6 bits4 bits5 bits
Fixed length = 15 bits
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