MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
21-2 Freescale Semiconductor
21.1.2 Overview
The eSCI allows asynchronous serial communications with peripheral devices and other CPUs. The eSCI
has special features which allow the eSCI to operate as a LIN bus master, complying with the LIN 2.0
specification.
Each of the eSCI modules can be independently disabled by writing to the module disable (MDIS) bit in
the module’s control register 2 (ESCIx_CR2). Disabling the module turns off the clock to the module,
although some of the module registers may be accessed by the core via the slave bus. The MDIS bit is
intended to be used when the module is not required in the application.
21.1.3 Features
The eSCI includes these distinctive features:
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• Configurable baud rate
• Programmable 8-bit or 9-bit data format
• LIN master node support
• Configurable CRC detection for LIN
• Separately enabled transmitter and receiver
• Programmable transmitter output parity
• Two receiver wake-up methods:
— Idle line wake-up
— Address mark wake-up
• Interrupt-driven operation
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection
• Two-channel DMA interface
21.1.4 Modes of Operation
The eSCI functions the same in normal, special, and emulation modes. It has a low-power module disable
mode.
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