Freescale Semiconductor MPC5553 - Features

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
18-8 Freescale Semiconductor
18.1.3.2 Debug Interface
Nexus level 3 debug support is available through the eTPU Nexus development interface (NDEDI). Refer
to Chapter 25, “Nexus Development Interface.”
18.1.4 Features
The eTPU includes these distinctive features:
• Up to 32 channels for each eTPU engine: each channel is associated with an I/O signal pair
— Enhanced input digital filters on the input pins for improved noise immunity. The eTPU digital
filter can use two samples, three samples, or work in continuous mode.
— Orthogonal channels, except for channel 0: each channel can perform any time function. Each
time function can be assigned to more than one channel at a given time, so each signal can have
any functionality. Channel 0 has the same capabilities of the others, but can also work with
special angle counter logic (see below).
— A link service request allows activation of a channel thread by request of another channel, even
between eTPU engines.
— A host service request allows activation of a channel thread by the MPC5553/MPC5554 core
request.
— Each channel has an event mechanism that supports single and double action functionality in
various combinations. It includes two 24-bit capture registers, two 24-bit match registers,
24-bit greater-equal or equal-only comparator.
• Two independent 24-bit time bases for channel synchronization
— The first time base may be clocked by the system clock with programmable prescaler division
from 2 to 512 (in steps of 2).
— The first time base can also be clocked by an external signal with programmable prescaler
divisions of 1 to 256.
— The second time base may be clocked by an external signal or by the system clock divided by 8.
— The second time base has a programmable prescaler that applies to all TCR2 clock inputs
except the angle counter.
— The second time base counter can work as an angle counter, enabling angle-based applications
to match angle instead of time.
— The second time base can alternatively be used as a pulse accumulator gated by an external
signal.
— Either time base can be written or read by either eTPU engine at any time.
— Either time base can be read, but not written, by the host.
— Both time bases can be exported or imported from engine to engine through the STAC (shared
time and counter) bus.
NOTE
An engine cannot export/import to/from itself. An engine cannot import a
time base and/or angle count if it is in angle mode.
• Event-triggered RISC processor (microengine)
— 2-stage pipeline implementation (fetch and execution), with separate instruction memory
(SCM) and data memory (SDM).
— Two-system-clock microcycle fixed-length instruction execution for the ALU.
— 16 Kbytes (MPC5554) or 12 Kbytes (MPC5553) of shared code memory (SCM).