Freescale Semiconductor MPC5553 - Detailed Memory Map (Control;Status Registers)

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
14-6 Freescale Semiconductor
14.3.2 Detailed Memory Map (Control/Status Registers)
Table 14-2 shows the FEC register memory map with each register address, name, and a brief description.
The base address of the FEC registers is 0xFFF4_C000.
NOTE
Some memory locations are not documented. The actual FEC memory map
is from 0xFFF4_C000 - 0xFFF4_C5FF. Also, some bits in otherwise
documented registers are not documented. These memory locations and bits
are not needed for the FEC software driver. They are used mainly by the
FEC subblocks for the FEC operation and happen to be visible through the
slave interface.
Errant writes to these locations can corrupt FEC operation. Because the FEC
is a system bus master, errant writes also can result in the corruption of any
memory mapped location in the system. However, even errant writes to
documented FEC memory locations can cause the same corruption.
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Table 14-2. FEC Register Memory Map
Address
Offset
(Base +)
Name Width
1
Description
0x0004 EIR 32 Interrupt Event Register
0x0008 EIMR 32 Interrupt Mask Register
0x0010 RDAR 32 Receive Descriptor Active Register
0x0014 TDAR 32 Transmit Descriptor Active Register
0x0024 ECR 32 Ethernet Control Register
0x0040 MMFR 32 MII Management Frame Register
0x0044 MSCR 32 MII Speed Control Register
0x0064 MIBC 32 MIB Control/Status Register
0x0084 RCR 32 Receive Control Register
0x00C4 TCR 32 Transmit Control Register
0x00E4 PALR 32 MAC Address Low Register
0x00E8 PAUR 32 MAC Address Upper Register + Type Field
0x00EC OPD 32 Opcode + Pause Duration Fields
0x0118 IAUR 32 Upper 32 bits of Individual Hash Table
0x011C IALR 32 Lower 32 Bits of Individual Hash Table
0x0120 GAUR 32 Upper 32 bits of Group Hash Table
0x0124 GALR 32 Lower 32 bits of Group Hash Table
0x0144 TFWR 32 Transmit FIFO Watermark
0x014C FRBR 32 FIFO Receive Bound Register